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WM8148 12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser
Production Data, April 1999, Rev 4.0
DESCRIPTION
The WM8148 is a 12-bit, 12MSPS analogue front end/ digitiser IC, which interfaces to colour or monochrome linear array CCDs or contact image sensors (CIS). The device includes all the signal conditioning circuitry required to process the analogue signals from the CCD or CIS prior to the internal ADC. Three signal-processing channels are included in the device. Each channel features reset level clamping, correlated double sampling (CDS), offset correction and programmable gain amplification (PGA). The output signal from each channel is then multiplexed into a high performance 12-bit analogue to digital converter (ADC). The reset level clamp and/or CDS functions can be selected or bypassed depending on the application. The WM8148 can be operated in several modes. The operational mode of the device, including the sampling scheme and power management is programmed via the serial/parallel control interface. Output data is presented in either 12-bit parallel or bytewide (8+4-bit) format.
FEATURES
* * * * * * * * * * * Correlated double sampling Programmable gain amplifier Programmable input clamp voltage Offset correction 12-bit, 12MSPS ADC Internal voltage reference 12-bit or 8+4 bit data output mode Single 5V supply or 5V analogue/3.3V digital supply Programmable sample timing Control interface compatible with previous Wolfson AFEs 48-pin TQFP package
APPLICATIONS
* * * * * * * Flatbed scanners Document scanners Multi-function peripherals (MFPs) Colour copiers Character recognition systems Linear array CCDs Contact image sensors (CIS)
BLOCK DIAGRAM
RLC (2) MCLK VSMP (5) (7) AVDD 1- 4 (41,28,27,3) DVDD1-2 (1,13) VRX VRB VRT (32) (29) (31)
CL R S V S
TIMING CONTROL
VREF/BIAS
WM8148
RINP (36)
CDS RLC 8 OFFSET DAC
+
PGA FULL . _ SCALE .2
+
(43) OEB
6
GINP (37)
CDS RLC 8 OFFSET DAC
+
PGA FULL . _ SCALE .2
+
MUX
12-BIT ADC
12/8 BIT MUX
OP[11:0] (9-12,14-21)
6
BINP (39)
CDS RLC 8 OFFSET DAC
+
PGA FULL . _ SCALE .2
+
(48) (34) (45) (46) (47) (42) (44) PNS OVRD SDI/DNA SCK/RNW SEN/STB NRESET SDO
6
VRLC (33)
RLC DAC 4
CONFIGURABLE SERIAL/PARALLEL CONTROL INTERFACE
(35,40,30,25,6) AGND1 - 5
(8,24,4,26) DGND1 - 4
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
(c)1999 Wolfson Microelectronics Ltd.
WM8148 PIN CONFIGURATION
SCK/RNW SDI/DNA SEN/STB NRESET AGND2 BINP AVDD1 NC GINP
Production Data
ORDERING INFORMATION
DEVICE XWM8148CFT/V TEMP. RANGE 0 to 70 C
o
PACKAGE 48-pin 1mm thick body TQFP
DVDD1 RLC AVDD4 DGND3 MCLK AGND5 VSMP DGND1 OP0 OP1 OP2 OP3
1 2 3 4 5 6 7 8 9
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
SDO OEB
PNS
RINP AGND1 OVRD VRLC VRX VRT AGND3 VRB AVDD2 AVDD3 DGND4 AGND4
10 11
25 12 13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTION
PIN 1 2 3 4 5 NAME DVDD1 RLC AVDD4 DGND3 MCLK TYPE Supply Digital input Supply Ground Digital input DESCRIPTION Digital supply (3.3V to 5V) for digital inputs and SDO. Selects whether reset level clamp is applied, active high. If RLC is required on every pixel then this pin can be tied high. Analogue supply (5V). Digital ground (0V). Master clock. This clock is applied at N times the input pixel rate (N = 12, 8, 6, or 4 dependent on input sampling mode). MCLK is divided internally by N to generate internal clocks and to provide the clock source for digital logic. Analogue ground (0V). Video sample synchronisation pulse. This pin may be either an input (default) or output. Input: This signal is pulsed externally to synchronise the WM8148's video input sample instant and the N-phase internal clock to CCD clocks and interface bus timing. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DGND1 OP0 OP1 OP2 OP3 DVDD2 OP4 OP5 OP6 OP7 OP8 OP9 OP10 OP11 Ground Digital output Digital output Digital output Digital output Supply Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Output: This signal is pulsed internally to flag the video input sample instant, to allow the CCD clocks and interface bus to be synchronised to the WM8148.
6 7
AGND5 VSMP
Ground Digital IO
WOLFSON MICROELECTRONICS LTD
NC NC DGND2
DVDD2
OP10 OP11
OP4 OP5
OP6
OP7 OP8
OP9
Digital ground (0V) for output drivers. 12-bit signal data output bus. Data is output MSB on OP[11] and LSB on pin OP[0]. See description of pins 14-21 for mode definitions.
Digital supply (3.3V-5V) for Digital IO pins and OP0 to OP3 12-bit bi-directional data bus. On pins OP[4] to OP[11], signal data is output if OEB = 0 and register write data is input if OEB = 1. There are five main modes: * Hi-Z: when OEB = 1 * Output 12-bit: twelve bit signal data output from bus * Output 8-bit muxed: signal data output on OP[11:4] at 2 ADC conversion rate * Input 8-bit: register write data input on OP[11:4] * Output 8-bit: register readback data output on OP[11:4]
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WM8148
PIN 22 23 24 25 26 27 28 29 30 31 32 33 NAME NC NC DGND2 AGND4 DGND4 AVDD3 AVDD2 VRB AGND3 VRT VRX VRLC Ground Ground Ground Supply Supply Analogue output Ground Analogue output Analogue output Analogue IO TYPE DESCRIPTION No internal connection. No internal connection. Digital ground (0V) for output drivers. Analogue ground (0V). Digital ground (0V). Analogue supply (5V). Analogue supply (5V).
Production Data
Lower reference voltage. This pin must be connected to AGND and VRT via decoupling capacitors. See Recommended External Components section for details. Analogue ground (0V). Upper reference voltage. This pin must be connected to AGND and VRB via decoupling capacitors. See Recommended External Components section for details. Input return bias voltage. This pin must be connected to AGND via decoupling capacitors. See Recommended External Components section for details. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. See Recommended External Components section for details. VRLC can be externally driven if programmed Hi-Z. Override pin. Typically tied low externally. The sense of this pin defines the device function on reset. Refer to the description of pin 42 for details. Analogue ground (0V). Red channel input video. Green channel input video. No internal connection. Blue channel input video. Analogue ground (0V). Analogue supply (5V). Reset input, active low. This signal forces a reset of all internal registers. Registers are set to defaults if pin OVRD is tied low. If pin OVRD is tied high then all registers are set to defaults except EN which is set to 1 and RLCEXT which is set to 0. This will turn on all analogue circuitry including the RLC DAC buffers driving the VRLC pin. Output enable control, all outputs disabled when OEB = 1. This pin must be externally connected. Serial Interface: register read-back, VSMP output, setup error flag or over-range flag (depending on control bits SDO [1:0]). Serial interface: serial input data signal. Serial interface: serial clock signal. Parallel Interface: Hi-Z, VSMP output, set-up error flag or over-range flag (depending on control bits SDO [1:0]). Parallel interface: High = data, Low = address. Parallel interface: High = OP[11:4] is output bus, Low = OP[11:4] is input bus (Hi-Z). Parallel interface: strobe, active low.
34
OVRD
Analogue input
35 36 37 38 39 40 41 42
AGND1 RINP GINP NC BINP AGND2 AVDD1 NRESET
Ground Analogue input Analogue input Analogue input Ground Supply Digital input
43 44
OEB SDO
Digital input Digital output
45 46
SDI/DNA SCK/RNW
Digital input Digital input
47 48
SEN/STB PNS
Digital input Digital input
Serial interface: enable pulse, active high.
Low = serial interface, High = parallel interface. This pin must be externally connected.
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WM8148 ABSOLUTE MAXIMUM RATINGS
Production Data
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount assembly and will be supplied in vacuum-sealed moisture barrier bags. It has been classified as having a Moisture Sensitivity Level of 2. CONDITION Analogue supply voltages: AVDD1 - 4 Digital supply voltages: DVDD1 - 2 Digital grounds: DGND1 - 4 Analogue grounds: AGND1 - 5 Digital inputs and SDO Digital outputs (not SDO) Digital IO pins RINP, GINP, BINP Other pins MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V MAX GND + 7V GND + 7V GND + 0.3V GND + 0.3V DVDD1 + 0.3V DVDD2 + 0.3V DVDD2 + 0.3V AVDD + 0.3V AVDD + 0.3V
Operating temperature range: TA Storage temperature Lead temperature (soldering, 10 seconds) Lead temperature (soldering, 2 minutes) Notes: * *
0C -50C
+70C +150C +260C +183C
GND denotes the voltage of any ground pin. AVDD denotes the voltage applied to any AVDD pin. AGND and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION Operating temperature range Digital input and output supply voltages Analogue supply voltages SYMBOL TA DVDD1 - 2 AVDD1 - 4 MIN 0 2.97 4.75 5 5 TYP MAX 70 5.25 5.25 UNITS C V V
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WM8148 ELECTRICAL CHARACTERISTICS
Production Data
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Overall System Performance Including 12-bit ADC, PGA, Offset and CDS Functions NO MISSING CODES GUARANTEED Full-scale input voltage range Max Gain Gain = 1.0 Min Gain Gain = 1.0 Gain = 1.0 DNL INL Gain = 1.0 Gain = 1.0 0.413 3.0 4.13 20 20 0.25 1.0 1.00 V V V mV mV LSB LSB
Zero-scale transition error Full-scale transition error Differential non-linearity Integral non-linearity ANALOGUE SPECIFICATION Input Multiplexer Channel to channel gain matching Input voltage range References Upper reference voltage Lower reference voltage Input return bias voltage Diff. reference voltage (VRT-VRB) Output resistance VRT, VRB, VRX Resistance VRT to VRB VRX Hi-Z leakage current VRLC/Reset-Level Clamp (RLC) RLC switching impedance VRLC Hi-Z leakage current VRLC DAC resolution VRLC DAC step VRLC short-circuit current VRLC output resistance VRT VRB VRX VRTB VIN
1 0 3.00 1.50 1.50 1.30 VRT, VRB, VRX buffers enabled VRT, VRB buffers disabled VRX buffer disabled 3.30 1.80 1.75 1.50 2 500 800 1100 1 75 VRLC = 0 to AVDD 4 AVDD = 5V VRLC = AVDD VRLC = 0V VRLC = other 8 DNL INL -0.25 -0.50 0.05 0.10 -200 200 6 GMAX GMIN 7.4 0.74 2 5 0.25 0.50 290 333 5 80 80 5 370 1 AVDD 3.60 2.10 2.00 1.70
% V V V V V A A bits mV/step mA bits LSB LSB mV mV bits V/V V/V %
Offset DAC Resolution Differential non-linearity Integral non-linearity Output voltage
Code 00(hex) Code FF(hex) Programmable Gain Amplifier. Monotonicity Guaranteed Resolution Max gain, each channel Min gain, each channel Gain error, each channel
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WM8148
Production Data
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER DIGITAL SPECIFICATIONS Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance output current Output rise/fall time Digital IO Pins Applied high level input voltage Applied low level input voltage High level output voltage Low level output voltage Low level input current High level input current High impedance output current Output rise/fall time Input capacitance SUPPLY CURRENTS Total supply current - active Total analogue supply current - active Total digital supply current - active Supply current - disabled IAVDD IDVDD CI VIH VIL VOH VOL IIL IIH IOZ CLOAD = 10pF 3 5 75 73 2 1 10 100 IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 1 1 1 0.8 DVDD2 0.2 DVDD2 V V V V A A A ns pF mA mA mA A VOH VOL IOZ CLOAD = 10pF 3 IOH = 1mA, DVDD = DVDD1 or DVDD2 IOL = 1mA DVDD - 0.5 0.5 1 V V A ns VIH VIL IIH IIL CI 5 0.8 DVDD1 0.2 DVDD1 1 1 V V A A pF SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM8148
INPUT VIDEO SAMPLING (EXTERNAL VSMP)
tP E R MCLK tV S M P S U VSMP INPUT tV S U VIDEO tV H tR S U tR H tV S M P H
Production Data
Figure 1 Input Video Timing (External VSMP)
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER MCLK period (dependent on mode selected) MCLK duty cycle VSMP set-up time VSMP hold time Video level set-up time Video level hold time Reset level set-up time Reset level hold time tVSMPSU tVSMPH tVSU tVH tRSU tRH SYMBOL tPER TEST CONDITIONS MIN 20.8 45 2 5 10 10 10 10 55 TYP MAX UNITS ns % ns ns ns ns ns ns
Notes: 1. tVSU and tRSU denote the set-up time required from when the input video signal has settled. 2. The reset sample point may be relative to either the rising or the falling edge of MCLK, depending on the setting of control bits RESREF[3:0]. 3. Parameters are measured at 50% of the rising/falling edge.
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WM8148
INPUT VIDEO SAMPLING (INTERNAL VSMP)
tPER MCLK tV S M P P D VSMP, OUTPUT tS D O P D SDO, OUTPUT tVSU VIDEO tVH tR S U tRH tSDOPD tVSMPPD
Production Data
Figure 2 Input Video Timing (Internal VSMP)
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER MCLK period MCLK duty cycle VSMP output propagation delay SDO output propagation delay Video level set-up time Video level hold time Reset level set-up time Reset level hold time tVSMPPD tSDOPD tVSU tVH tRSU tRH CLOAD = 10pF CLOAD = 10pF 10 10 10 10 SYMBOL tPER TEST CONDITIONS MIN 20.8 45 15 20 55 25 35 TYP MAX UNITS ns % ns ns ns ns ns ns
Notes: 1. tVSU and tRSU denote the set-up time required from when the input video signal has settled. 2. The reset sample point may be relative to either the rising or the falling edge of MCLK, depending on the setting of control bits RESREF[3:0]. 3. Parameters are measured at 50% of the rising/falling edge.
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WM8148
RESET LEVEL CLAMP
MCLK
Production Data
VSMP t RLCSU RLC = 0 RLC = 1 t RLCH
Figure 3 Reset Level Clamp Control Timing
t PER MCLK t RLCPD CL
MODE 8-13 SMALL = 0
t RLCPD ON t RLCPD t RLCPD ON t RLCPD t RLCPD ON t RLCPD t RLCPD ON OFF OFF OFF OFF
OFF
CL
MODE 8-13 SMALL = 1
OFF
CL
MODE 0-5 SMALL = 0
OFF
CL
MODE 0-5 SMALL = 1
OFF
Figure 4 Internal Clamp Signal (CL) Timing
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER MCLK period Propagation delay Set-up time Hold time SYMBOL tPER tRLCPD tRLCSU tRLCH 10 10 TEST CONDITIONS MIN 20.8 15 TYP MAX UNITS ns ns ns ns
Notes: 1. Internal clamp signal (CL) timing may be relative to either the falling or rising edge of MCLK depending on the setting of control bits RESREF[3:0]. 2. Parameters are measured at 50% of the rising/falling edge.
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WM8148
OUTPUT DATA
Production Data
OEB t PZE OP[11:0] Hi-Z t PEZ Hi-Z
Figure 5 Output Data Enable Timing
MCLK t PD FDEL[1:0] = 01 OP[11:0] t PD FDEL[1:0] = 00 DEFAULT OP[11:0] t PD OP[11:0] t PD FDEL[1:0] = 11 OP[11:0]
FDEL[1:0] = 10
Figure 6 Output Data Timing (Including Fine Latency Control By FDEL[1:0])
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER Output propagation delay Output enable time Output disable time SYMBOL tPD tPZE tPEZ TEST CONDITIONS IOH = 1mA, IOL = 1mA MIN 10 TYP 20 MAX 30 15 15 UNITS ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge.
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WM8148
SERIAL INTERFACE
tS P E R SCK tS S U SDI tS C E tS E W tS E C tS H tS C K L tS C K H
Production Data
SEN tS E S D tS C S D tS C S D Z
SDO
Figure 7 Serial Interface Timing
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK to SEN set-up time SEN to SCK set-up time SEN pulse width SEN low to SDO out SCK low to SDO out SCK low to SDO high impedance SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCE tSEC tSEW tSESD tSCSD tSCSDZ TEST CONDITIONS MIN 83.3 20 20 10 10 20 20 50 35 35 25 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge.
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WM8148
PARALLEL INTERFACE
tS T B STB tA S U D[11:4]
ADC DATA OUT
Production Data
tA H
ADDRESS IN
tD S U
DATA IN
tD H Z
tS T D O
ADC DATA OUT
tS T A O
DATA OUT ADC DATA OUT
Z
tA D L S DNA tO P Z RNW
tA D L H
tA D H S
tA D H H
tO P D
Figure 8 Parallel Interface Timing
TEST CONDITIONS AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 48MHz unless otherwise stated (AVDD denotes the voltage applied to all AVDD pins). PARAMETER RNW Low to OP[11:4] Hi-Z. Address set-up time to STB Low DNA Low set-up time to STB Low Strobe Low time Address hold time from STB High DNA Low hold time from STB High Data set-up time to STB Low DNA High set-up time to STB Low Data hold time from STB High Data High hold time from STB High RNW High to OP[11:4] output Data output propagation delay from STB Low ADC data out propagation delay from STB High SYMBOL tOPZ tASU tADLS tSTB tAH tADLH tDSU tADHS tDH tADHH tOPD tSTDO tSTAO 10 10 50 10 10 10 10 10 10 35 35 35 TEST CONDITIONS MIN TYP MAX 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge.
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WM8148 TYPICAL OVERALL SYSTEM PERFORMANCE
(INCLUDING CDS, PGA AND ADC BLOCKS) DNL VS CODES
22
1.5 1.5
Production Data
INL VS CODES
5.00 5.00 4.00 4.00 3.00 3.00
11
2.00 2.00
0.5 0.5
DNL (LSB's) DNL (LSB)
00
INL (LSB)
1.00 1.00
-0.5 -0.5
-1 -1
-1.5 -1.5
-2 -2 0 0 512 512 1024 1024 1536 1536 2048 2048 2560 2560 3072 3072 3584 3584 4096 4096
INL (LSBs)
0.00 0.00
-1.00 -1.00 -2.00 -2.00 -3.00 -3.00 -4.00 -4.00 -5.00 -5.00 0 0 512 512 1024 1024 1536 1536 2048 2048 2560 2560 3072 3072 3584 3584 4096 4096
Output Data Codes Output Data Code s
Output Output Data Codes Data Codes
Figure 9 DNL Vs Output Data Codes (MODE 1, MCLK = 32MHz, AVDD = 5V, DVDD = 3.3V)
Figure 10 INL Vs Output Data Codes (MODE 1, MCLK = 32MHz, AVDD = 5V, DVDD = 3.3V)
GROUNDED-INPUT HISTOGRAMS
1 RMS noise = 0.26 LSB 1
40.57% 94.36% RMS noise = 0.95 LSB
1
HITS (percent) (of 262144 total )
26.49%
HITS (percent) (of 262144 total)
20.90%
0
0 4.58% 0.00% 0 N-2 N-1 N Output Data Code N+1 N+2 N-3 N-2 N-1 N N+1 2.85% 2.79% 0.00% 0.40%
6.34%
0.63% N+2 N+3
Output Data Code
Figure 11 Unity Gain Histogram (MODE 1, MCLK = 32MHz, GAIN = 1, AVDD = 5V, DVDD = 3.3V)
Figure 12 Maximum Gain Histogram (MODE 1, MCLK = 32MHz, GAIN = 7.4, AVDD = 5V, DVDD = 3.3V)
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WM8148 SYSTEM INFORMATION
Production Data
Figure 13 shows a system block diagram for a typical application. The CCD image sensor contains three parallel linear arrays of sensor elements (sensitive to Red, Green, and Blue light respectively). The Red, Green and Blue output signals are each applied to the RINP, GINP and BINP channel inputs respectively of the WM8148. Each of these channels provide gain adjust, for compensation of sensor sensitivity and offset adjust for nulling out d.c. offset voltages. The outputs of these three channels are time multiplexed into a single 12-bit resolution ADC. The digital output is then transferred to a digital ASIC or other digital processor. The corrected data can then be compressed if required before being output to a data storage device or a monitor.
R
BUFFER
RINP CLOCKS
S E N S O R
G
BUFFER
GINP
WM8148
DATA
CONTROL I/F B
BUFFER
SYSTEM ASIC
BINP
SENSOR TIMING
Figure 13 System Diagram
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WM8148 DEVICE DESCRIPTION
INTRODUCTION
Production Data
The WM8148 samples up to three analogue inputs simultaneously, conditions these signals and converts each resulting analogue signal to a 12-bit digital word. A block diagram is shown on page 1. Each of the three input channels consists of an Input Sampling block (CDS/RLC), an 8-bit programmable Offset DAC, and a 6-bit Programmable Gain Amplifier (PGA). The outputs from the three channels are multiplexed into a 12-bit ADC. The digital output from the ADC is presented on a 12-bit wide bi-directional bus. A high-speed (up to 48MHz) master clock, MCLK, and a per-pixel synchronisation pulse, VSMP, drive a shared Timing Control block to generate input sampling signals and other internal clocks. Alternatively the device can operate from MCLK only, outputting VSMP synchronisation pulses to the rest of the system. An internal reference provides buffered voltages VRT, VRB and VRX. A 4-bit DAC (RLC DAC) provides a programmable buffered voltage at pin VRLC for use as an input signal reference level or an input clamp voltage. The operation of the device is controlled by internal control registers, which can be read from and written to via a Digital Management Interface (DMI) in either serial or parallel mode.
INPUT SAMPLING
Figure 14 shows the configuration of the Input Sampling Block for the red channel. (The green and blue channels are the same.)
RLC
MCLK
VSMP
TIMING CONTROL CL RS VS
From Control Interface
RINP
S/H RLC CDS
S/H
+
+
INPUT SAMPLING BLOCK FOR RED CHANNEL
To Offset DAC
MODE[0]
VRLC
4-BIT RLC DAC
From Control Interface
Figure 14 Input Sampling Block - Configuration for Red Channel This block contains switches to perform Reset Level Clamping (RLC) and Correlated Double Sampling (CDS). Sample/Hold blocks sample the video and reset/reference levels of the input waveform, and pass the difference signal on to the rest of the channel. Internal clocks VS and RS define the timing of the sampling of the video signal and the reset/reference level respectively. When enabled by control input pin RLC, internal signal CL clamps the input pin RINP to the voltage on pin VRLC, which is driven either externally or from the 4-bit RLC DAC. The detailed timing of the internal clock signals CL, VS, and RS, with respect to VSMP and MCLK, is controlled by the Timing Control block as programmed via the Digital Management Interface (DMI).
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WM8148
INPUT SAMPLING MODES
Production Data
To suit different sensors and applications, the WM8148 can sample one, two, or three channels simultaneously, at the rate of the VSMP clock. In each case there are two possible ratios of VSMP frequency to the MCLK master clock frequency, and a choice of whether to use CDS. Table 1 summarises the options available, including the respective maximum sample rates. The mode of operation is set by the Control Register bits MODE[3:0] as shown. Note MODE[0] defines whether or not CDS is activated. MAX SAMPLE RATE PER CHANNEL (VSMP) MSPS Three-channel (8-phase) Three-channel (12-phase) Two-channel (6-phase) Two-channel (8-phase) One-channel CDS One-channel non-CDS 4 4 5.33 6 6.66 10 8 12 6 8 6 4 MCLK/VSMP FREQUENCY RATIO MAX MCLK FREQENCY MAX OUTPUT RATE MODE NUMBER (MODE[3:0])
MHz 32 48 32 48 40 40
MSPS 12 12 10.66 12 6.66 10
CDS 0 8 4 12 2 N/A
NONCDS 1 9 5 13 N/A 3
Table 1 Modes of Operation If an external VSMP signal is not available, the WM8148 can be configured to output a synchronisation pulse to the system by setting control bit FREE. The internally generated signal is presented on the VSMP and/or SDO pins depending on the settings of the control bits VSMPOP and SDO[1:0].
CORRELATED DOUBLE SAMPLING (CDS)
The input signal can be sampled in two ways: Correlated Double Sampling (CDS), or non-CDS. CDS operation is summarised in Figure 15. The video signal processed is the difference between the voltage applied at the RINP input when RS turns off and the voltage at the RINP input when VS turns off, i.e. the difference between reset and video levels from the same pixel of the input signal. This method of sampling is recommended as it removes common-mode noise.
V RS
V VS
RS
VS
Figure 15 CDS Reset and Video Level Sampling In non-CDS modes, RS and VS occur simultaneously. VS samples the video signal, while RS samples the reference level applied to the VRLC pin. The video signal processed is the difference between these samples (VRS-VVS). The voltage (VVRLC), on pin VRLC, may be driven externally or internally by the RLC DAC. In these modes d.c. variations of the input signal are not rejected.
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RESET LEVEL CLAMPING (RLC)
Production Data
If the sensor output voltage is within the input range of the WM8148, the sensor may be d.c. coupled into the WM8148 either directly or via a buffer. If the output from the sensor is outside the input range of the WM8148, the signal has to be connected via a capacitor, CIN, and the d.c. bias conditions must be defined on the WM8148 side of the capacitor (at RINP). Setting of the d.c. bias conditions is best performed by Reset-Level Clamping, activated by pin RLC. Reset-Level Clamping is compatible with both CDS and non-CDS operating modes. A typical configuration is shown in Figure 16.
RLC
MCLK
VSMP
TIMING CONTROL CL RS VS
FROM CONTROL INTERFACE
C IN
S/H +
RINP 1
RLC
2
+
S/H CDS INPUT SAMPLING BLOCK FOR RED CHANNEL
TO OFFSET DAC
EXTERNAL VRLC VRLC
MODE[0] 4-BIT RLC DAC
FROM CONTROL INTERFACE
Figure 16 Reset-Level Clamping Circuitry When the clamp pulse, CL, is active, the voltage on the WM8148 side of CIN, at RINP, will be forced equal to the VRLC voltage, VVRLC, by switch 1. When the CL pulse turns off, the RINP voltage will initially remain at VVRLC, but any subsequent variation in sensor voltage appearing at the sensor side of CIN will couple through CIN to RINP. Switch 2 determines whether the RS level is taken from the incoming signal (CDS operation) or the VRLC pin (non-CDS operation). Figure 17 demonstrates the case of a typical CCD waveform, with CL applied during the reset period.
MCLK
VSMP
RLC
1
X Programmable Delay
X
0
X
X
0
X
CL
Input Video
r,g,b RLC on this pixel
r,g,b
r,g,b No RLC on this pixel
Figure 17 Relationship of RLC pin, MCLK and VSMP to Internal Clamp Pulse, CL The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position and duration of CL is adjustable by control bits RESREF[3:0] and SMALL.
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Production Data If pin RLC is tied high then reset level clamping is applied on every pixel. Alternatively, for line-byline clamping, pin RLC can be driven high at the start of a line (during the dummy black pixel output), then driven low for the remainder of the line. If pin RLC is tied low then reset level clamping will not be applied. The VRLC voltage, to which the reset level is clamped, can be defined either by an external voltage or internally via the 4-bit programmable RLC DAC. To clamp to an internally defined voltage RLCEXT must be set to `0'. Control bits RLCV[3:0] then program the RLC DAC to a voltage ranging between 0V and AVDD linearly over 15 steps. The voltage from the RLC DAC will also be presented on pin VRLC which should be decoupled to analogue ground. Alternatively, by setting control bit RLCEXT to `1', the RLC DAC is disconnected and the VRLC pin is driven externally to any voltage between 0V and AVDD.
PROGRAMMABLE OFFSET DAC
The output from the Input Sampling Block is added to the output of an 8-bit Offset DAC to allow cancellation of offsets in sensor black level and input offsets of the WM8148. The DACs cover a range of 200mV in 255 equal steps of 1.57mV, programmable via the DMI. Programming 00(hex) to the DAC gives an offset adjustment of -200mV, FF(hex) adjusts the input signal by +200mV.
PROGRAMMABLE GAIN AMPLIFIERS (PGA)
When the black level has been adjusted using the Offset DAC, the gain of the PGA can be programmed to amplify the white level signal to cover the full ADC range (3V). Figure 18 shows a graph of the PGA gain response. This gain curve is non-linear, with gain given by: Gain = 52 / {70 - PGA[5:0](dec)} This gives a gain ranging from 0.74 times to 7.4 times over 63 steps, with minimum gain corresponding to 00(hex) and maximum gain corresponding to 3F(hex). Figure 19 shows the PGA gain code settings required, for PGA input voltages from 0.4V to 4.0V, to produce a PGA output equivalent to the full scale input range of the ADC (3V).
8 7 4 6 5 Gain 4 3 2 1 1 0 12 15 18 21 24 27 30 33 36 00 03 06 09 2D 39 0C 3C 0F 1B 1E 2A 3F 0 0C 2D 3C 00 03 06 09 12 15 18 21 24 27 30 33 36 0F 39 1B 1E PGA Gain code, PGA[5:0] (hex) 2A 3F PGA Input Voltage (V) PGA Gain code, PGA[5:0] (hex) 5
3
2
Figure 18 PGA Gain Response
Figure 19 PGA Input vs Gain Code for Full Scale ADC Input
ANALOGUE TO DIGITAL CONVERTER (ADC)
The output of the PGA is applied to a high performance ADC. The differential signal from the PGA ranges from 0V (black level) to either +3V or -3V (white level), depending on the polarity of the input signal to the device. Control bits PGAFS[1:0] are used to configure the input of the ADC to accept the desired input signal range. This is achieved by adding 0, + or - half of the full scale voltage to the ADC input signal on a channel-by-channel basis, as shown in the block diagram on page 1. Table 2 shows the PGAFS[1:0] settings required for different video signal types.
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VIDEO SIGNAL TYPE Positive-going, e.g. many CIS Negative-going, e.g. CCDs Bipolar DIFFERENTIAL SIGNAL RANGE BLACK 0V 0V -1.5V WHITE 3V -3V +1.5V 11 10 00, 01 Black = 0 White = 4095 Black = 4095 White = 0 Black = 0 White = 4095 PGAFS[1:0] OUTPUT CODE INVOP = 0
Production Data
OUTPUT CODE INVOP = 1 Black = 4095 White = 0 Black = 0 White = 4095 Black = 4095 White = 0
Table 2 PGAFS[1:0] Setting for Video Signal Types If the signal exceeds the chosen range, it is clipped and the error flag OVRNG is set, which may be output via the SDO or OP pins.
OVERALL SIGNAL FLOW SUMMARY
Figure 20 represents the processing of the video signal through the WM8148. The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 12-bit unsigned digital output, D1. The digital output is then inverted if required, through the OUTPUT INVERT BLOCK to produce D2.
OUTPUT INVERT BLOCK
INPUT SAMPLING OFFSET DAC P G A BLOCK BLOCK BLOCK
ADC BLOCK V 3 x 4095/V F S ) = +0 codes if PGAFS[1:0]=11 +4095 codes if PGAFS[1:0]=10 +2047 codes if PGAFS[1:0]=0x
V1
V IN MODE[0] = 0 VRESET MODE[0] = 1 VVRLC RLCEXT=1 RLCEXT=0
Offset DAC
V2
++
V3
D1
digital
D2
OP[11:0]
+
-
X
analog
D2 = D1 if INVOP = 0 D2 =4095-D1 if INVOP = 1 PGA gain A = 52/(70-PGA[5:0]) 200mV*(DAC[7:0]-127.5)/127.5 V IN is RINP or GINP or BINP V R E S E T is V IN sampled during reset clamp VRLC is voltage applied to VRLC pin MODE[0], RLCEXT,RLCV[3:0], DAC[7:0], PGA[5:0], PGAFS[1:0] and INVOP are set by programming internal control registers. MODE[0]=0 for CDS, 1 for non-CDS
RLC DAC
AVDD*RLCV[3:0]/15
Figure 20 Overall Signal Flow
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CALCULATING OUTPUT FOR ANY GIVEN INPUT
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The following equations describe the processing of the video and reset level signals through the WM8148. INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING If MODE[0] = 0, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. V1 = VIN - VRESET Eqn. 1
If MODE[0] = 1, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. V1 = VIN - VVRLC Eqn. 2
If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC. If RLCEXT = 0, VVRLC is the output from the internal RLC DAC. VVRLC = AVDD RLCV[3:0] / 15 Eqn. 3
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the Offset DAC output. V2 = V1 + 200mV (DAC[7:0]-127.5) / 127.5 Eqn. 4
PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, V3 = V2 52/(70- PGA[5:0]) Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then converted to a 12-bit unsigned number, with input range configured by PGAFS[1:0]. D1[11:0] = INT{ (V3 /VFS) 4095} + 2047 D1[11:0] = INT{ (V3 /VFS) 4095} D1[11:0] = INT{ (V3 /VFS) 4095} + 4095 where the ADC full-scale range, VFS, = 3V. OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP. D2[11:0] = D1[11:0] D2[11:0] = 4095 - D1[11:0] (INVOP = 0) (INVOP = 1) Eqn. 9 Eqn. 10 PGAFS[1:0] = 00 or 01 PGAFS[1:0] = 11 PGAFS[1:0] = 10 Eqn. 6 Eqn. 7 Eqn. 8
OUTPUT DATA FORMAT
MULTIPLEXED AND NON-MULTIPLEXED OUTPUT FORMAT Data is output from the device, by default, as a 12-bit wide word on OP[11:0]. The output changes on every Nth negative-going edge of MCLK where N = 2, 4, or 6 according to the video sampling mode. This is shown as byte C in Figure 21. If control bit MUXOP is set high, data is output in a 2 x 8-bit word format, with data changing every Nth negative-going edge of MCLK, where N = 1, 2, or 3 according to video sampling mode. This is shown as bytes A and B in Figure 21. Data is presented on pins OP[11:4] at twice the output pixel rate. Bits CC[1] and CC[0] are used to indicate which channel the ADC input was taken from. Table 3 shows the channels corresponding to the CC[1:0] bit values. Bits TVIOL and OVRNG of byte B are Error Flags, these are described below.
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OP[11:4] MUXOP=1 A B
Production Data
OP[11:0] MUXOP=0
C
Figure 21 Output Data for 2 x 8-bit and 12 bit Output. Where: A = < d11, d10, d9, d8, d7, d6, d5, d4 > B = < d3, d2, d1, d0, TVIOL, CC[1], CC[0], OVRNG > C = < d11, d10, ... d1, d0 > COLOUR CODE BITS CC[1] 0 0 1 CC[0] 0 1 0 Red Green Blue CHANNEL
Table 3 Colour Code Bits CC[1:0] ERROR FLAGS The two error flags are: TVIOL: This goes high if the reset sample and clamp positions set up in bits RESREF[3:0], are inconsistent with the selected mode of operation. OVRNG: This goes high if the input to the ADC exceeds its input range. These flags are output in byte B of multiplexed-mode parallel output data as above. Each is also available via the SDO pin if so configured via the SDO[1:0] register bits. LATENCY Default latency from the last rising edge of MCLK during the VSMP pulse to data output depends on the chosen Input Sampling Mode. To align pixel outputs with post processing circuitry and to reduce interaction with video sampling instances, the latency through the WM8148 device can be adjusted by Control bits DEL[1:0] and FDEL[1:0].
DIGITAL MANAGEMENT INTERFACE (DMI)
The DMI is used to write contents to and read back contents from the internal registers in either serial or parallel mode. The PNS pin is tied low for serial and high for parallel mode.
SERIAL INTERFACE
REGISTER WRITE
SCK
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
Address SEN
Data Word
Figure 22 Serial Interface Register Write
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Production Data Figure 22 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode. REGISTER READ-BACK
SCK
SDI
a5
1
a3 a2 a1 a0
x
x
x
x
x
x
x
x
Address SEN
Data Word
SDO
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word OEB
Figure 23 Serial Interface Register Read-back Register read-back is initiated by writing to the serial bus as described, but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK), provided control bits SDO[1:0] = 00. If SDO[1:0] is not set to 00 then error flags will be output instead of the register contents. Note that if SDI and SDO are not connected together, the next word may be read in to SDI while the previous word is still being output on SDO. Alternatively, the user may tie the SDI and SDO pins together to make a 3-wire serial interface. The user must ensure that the circuit driving SDI is Hi-Z while the SDO pin is active. Pin OEB must be low to enable the output data word to be output.
PARALLEL INTERFACE
REGISTER WRITE
STB
Driven by WM8148 Driven Externally Hi-Z Address Data Hi-Z Driven by WM8148 Normal Output Data
OP[11:4]
Normal Output Data
DNA
RNW
Figure 24 Parallel Interface Register Write The parallel interface uses bits [11:4] of the OP bus and the STB, DNA and RNW pins. Pin RNW must be low during a write operation. The DNA pin defines whether the data byte is address (low) or data (high). The 6-bit address (a5, 0, a3, a2, a1, a0) is input into OP[9:4], LSB into OP[4], (OP[10] and OP[11] are ignored) when DNA is low, then the 8-bit data word is input into OP[11:4], LSB into OP[4], when DNA is high. The data bus OP[11:4] for both address and data is latched in during the low period of STB. Note all valid registers have address bit a4 equal to 0. WOLFSON MICROELECTRONICS LTD
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REGISTER READ-BACK
Production Data
STB
Driven by WM8148 Hi-Z Driven Externally Address Hi-Z Read Data Driven by WM8148 Normal Output Data
OP[11:4]
Normal Output Data
DNA
RNW
Figure 25 Parallel Interface Register Read-back Register read-back is initiated by writing the 6-bit address (a5, 1, a3, a2, a1, a0) into OP[9:4] by pulsing the STB pin low. Note that a4 = 1 and pins RNW and DNA are low. When RNW and DNA are high and STB is strobed again, the contents (d7, d6, d5, d4, d3, d2, d1, d0) of the corresponding register (a5, 0, a3, a2, a1, a0) will be output on OP[11:4], LSB on pin OP[4]. Until STB is pulsed low, the current contents of the ADC (shown as Normal Output Data) will be present on OP[11:4].
OUTPUT ENABLE
When high, pin OEB makes pins OP[11:0] Hi-Z regardless of other pin settings. Therefore when the WM8148 is outputting normal ADC data, or during register read, pin OEB must be set to `0'. During register write, pin RNW set to `0' ensures that the outputs are Hi-Z, therefore pin OEB is `don't care'. Table 4 shows the state of pins OP[11:0] for possible settings of OEB, RNW and STB. OEB 1 x 0 0 RNW x 0 1 1 STB x x 0 1 OP[11:0] Hi-Z Hi-Z Read register data Read ADC data
Table 4 State of OP[11:0] During Register Read/Write
POWER MANAGEMENT
Power management for the WM8148 is performed via the DMI. The device can be powered on or off completely by the control bit EN. Alternatively, when control bit SELEN is high, only blocks selected by further control bits SENBL[7:0] are powered up. This allows the user to optimise power dissipation in certain modes, or to define intermediate standby modes to allow a quicker recovery into a fully active state. EN 0 1 x SELEN 0 0 1 Device completely powers down. Device completely powers up. Only blocks with respective SENBL bit high go/remain active.
Table 5 Power Down control Control bit RLCEXT is used to disable the RLC DAC, regardless of EN or SENBL[7:0]. If this option is taken, pin VRLC can be driven externally for reset level clamping. One-channel and Two-channel sampling modes do not automatically power down unused PGAs, the appropriate SENBL bits should be set during initialisation to save power. The WM8148 will still operate normally if the unused blocks are not powered down. All the internal registers maintain their previously programmed value in power down modes, and the DMI inputs remain active.
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REGISTER RESET
RESET ON POWER UP
Production Data
To set the registers to their default values, pin NRESET must be held low during power-up. If pin OVRD is also held low, all of the registers will be set to their default values including bits SELEN and EN which will disable all of the analogue circuitry. If pin OVRD is held high during power up with pin NRESET held low, all of the registers will be set to their default value with the exception of EN and RLCEXT, which will enable all of the analogue circuitry in the device. RESET DURING OPERATION During device operation, pulsing NRESET low will reset all of the registers depending on the polarity of the OVRD pin as above. The registers may also be reset by writing to bits SRES[1:0]. This allows reset of: 1) 2) 3) Only the PGA Gains and Offset DAC Values registers, All registers except power-management registers SELEN, EN, and SENBL, or All registers, equivalent to the NRESET function.
REFERENCE VOLTAGES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLC DAC also requires decoupling at pin VRLC. Peak sink and source currents of the reference buffers are typically between 1mA and 6mA, depending on output voltage and current polarity. This limits the slew-rate into the decoupling capacitors on power-up. When disabled, the buffers become high-impedance (I < 1A), so the decoupling capacitor voltage will not drop much during short (< 100ms) disable durations.
DETAILED MODE TIMING DIAGRAMS
The following diagrams show Input Signal Sampling Diagrams, Output Data Timing and Reset Sample/Clamp Positions for each mode of the WM8148. INPUT SIGNAL SAMPLING DIAGRAMS These diagrams show the required MCLK and VSMP (externally or internally generated) signals. From these signals, internally generated signals VS and RS are used to sample the video and reset levels (in CDS modes) respectively. In non-CDS modes, the reference level is sampled simultaneously with VS. The position of the sampling point is indicated by the vertical lines which run from the sensor output waveform to the respective VS or RS sampling points, and by the inclusion of the arrow on the falling edge of the VS or RS pulse. Also shown is MCLK timing, which counts the number of MCLK periods in total, and MCLK phase, which counts the number of MCLK periods between each VSMP pulse. Note that the duration of the VSMP pulse must not include more than one MCLK rising edge, as this will reset the phase timing. The output waveforms are included. The position of the RS pulse is programmable, therefore the RESREF[3:0] position for each diagram has been included. OUTPUT DATA TIMING DIAGRAMS The output timing diagrams are used to calculate the latency through the device, which is dependent on the operating mode. The latency can be programmed using the DEL[1:0] bits in setup register 4. Output timing and latency does not depend on the RESREF[3:0] control bits. As an example, Figures 26 and 27 show that a sample taken on the rising edge of MCLK at time 1, will emerge from the device on the falling edge of MCLK at time 19, i.e. a latency of 18.5 MCLK periods (DEL = 00). RESET SAMPLE/CLAMP POSITIONS In CDS modes, control bits RESREF[3:0] control the position of the reset sampling point, RS, and the clamp pulse point, CL, if reset level clamping is selected. In non-CDS modes, control bits RESREF[3:0] control the position of CL only, if reset level clamping is selected. These diagrams show the positions to which the sampling or clamping pulse can be adjusted for each mode. Care must be taken to adjust the RS position to one that will ensure that the reset sample and/or clamp point will be taken at the most appropriate moment during the reset portion of the input signal. WOLFSON MICROELECTRONICS LTD
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WM8148
THREE-CHANNEL (8-PHASE) - MODES 0 AND 1
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=4) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) Reset Video Reset Video
Production Data
-4 4
-3 5
-2 6
-1 7
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 0
9 1
Figure 26 Modes 0 and 1 Input Signal Sampling
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=4) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11)
Reset
Video
Reset
Video
19 3
20 4
21 5
22 6
23 7
24 0
25 1
26 2
27 3
28 4
29 5
30 6
31 7
32 0
33 1
2 2
R
G R G R
B B G R G B B
Figure 27 Modes 0 and 1 Output Data Timing
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Phase MCLK VSMP VS 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6
Production Data
7 0 1
F CL (RESREF=0) F CL (RESREF=1) R S /CL (RESREF=2) R S /CL (RESREF=3) R S /CL (RESREF=4) R S /CL (RESREF=5) R S /CL (RESREF=6) R S /CL (RESREF=7) R S /CL (RESREF=8) R S /CL (RESREF=9) R S /CL (RESREF=10)
F Invalid RESREF positions in CDS Mode (Mode 0)
Figure 28 Modes 0 and 1 Reset Sample/Clamp Positions
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ONE-CHANNEL CDS - MODE 2
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S (RESREF=2) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) -4 2 Reset Video Reset Video
Production Data
Reset
-3 3
-2 4
-1 5
0 0
1 1
2 2
3 3
4 4
5 5
6 0
7 1
8 2
9 3
Figure 29 Mode 2 Input Signal Sampling
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S (RESREF=2) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) 49 1 50 2
Reset
Video
Reset
Video
Reset
51 3
52 4
53 5
54 0
55 1
56 2
57 3
58 4
59 5
60 0
61 1
62 2
RGB RGB RGB RGB
Figure 30 Mode 2 Output Data Timing
Phase MCLK VSMP VS 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
R S /CL (RESREF=2) R S /CL (RESREF=3) R S /CL (RESREF=4) R S /CL (RESREF=5) R S /CL (RESREF=6)
Figure 31 Mode 2 Reset Sample/Clamp Positions
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ONE-CHANNEL NON-CDS - MODE 3
CCD Output Video Video Video
Production Data
Time (MCLK) Phase MCLK VSMP VS CL (RESREF=0) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11)
-4 0
-3 1
-2 2
-1 3
0 0
1 1
2 2
3 3
4 0
5 1
6 2
7 3
Figure 32 Mode 3 Input Signal Sampling
CCD Outputs Time (MCLK) Phase MCLK VSMP VS CL (RESREF=0) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) 34 2 35 3 36 0
Video
Video
Video
37 1
38 2
39 3
40 0
41 1
42 2
43 3
44 0
45 1
RGB RGB RGB RGB
Figure 33 Mode 3 Output Data Timing
2 MCLK VSMP VS
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
CL (RESREF=0) CL (RESREF=1) CL (RESREF=2)
Figure 34 Mode 3 Reset Sample/Clamp Positions WOLFSON MICROELECTRONICS LTD
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TWO-CHANNEL (6-PHASE) - MODES 4 AND 5
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=2) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) -4 2 Reset Video Reset Video
Production Data
Reset
-3 3
-2 4
-1 5
0 0
1 1
2 2
3 3
4 4
5 5
6 0
7 1
8 2
9 3
Figure 35 Modes 4 and 5 Input Signal Sampling
Reset Video Reset Video
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=2) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) R 19 1 20 2
21 3
22 4
23 5
24 0
25 1
26 2
27 3
28 4
29 5
30 0
31 1
32 2
G R G R G R G
Figure 36 Modes 4 and 5 Output Data Timing
4 MCLK VSMP VS 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
F CL (RESREF=0) F CL (RESREF=1) R S /CL (RESREF=2) R S /CL (RESREF=3) R S /CL (RESREF=4) R S /CL (RESREF=5) R S /CL (RESREF=6)
F Invalid RESREF positions in CDS mode (Mode 4)
Figure 37 Modes 4 and 5 Reset Sample/Clamp Positions WOLFSON MICROELECTRONICS LTD
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WM8148
THREE CHANNEL (12-PHASE) - MODES 8 AND 9
CCD Outputs Reset Video Reset
Production Data
Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=6) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11)
-6 6
-5 7
-4 8
-3 9
-2 10
-1 11
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 0
13 1
Figure 38 Modes 8 and 9 Input Signal Sampling
CCD Outputs
Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=6) O/P (DEL=00 O/P (DEL=01) O/P (DEL=10) O/P (DEL=11)
33 34 9 10
35 11
36 0
37 38 12
39 3
40 4
41 42 56
43 7
44 8
45 46 9 10
47 11
48 0
49 1
50 2
51 3
52 4
53 5
54 6
55 7
56 8
57 9
58 10
59 11
R
G R
B G R B G R B G B
Figure 39 Modes 8 and 9 Output Data Timing
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
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WM8148
10 MCLK VSMP VS 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2
Production Data
3 4 5
F CL (RESREF=0) F CL (RESREF=1) R S /CL (RESREF=2) R S /CL (RESREF=3) R S /CL (RESREF=4) R S /CL (RESREF=5) R S /CL (RESREF=6) R S /CL (RESREF=7) R S /CL (RESREF=8) R S /CL (RESREF=9) R S /CL (RESREF=10) R S /CL (RESREF=11) R S /CL (RESREF=12) R S /CL (RESREF=13) R S /CL (RESREF=14)
F Invalid RESREF positions in CDS mode (Mode 8)
Figure 40 Modes 8 and 9 Reset Sample/Clamp Positions
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
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WM8148
TWO-CHANNEL (8-PHASE) - MODES 12 AND 13
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=2) O/P (DEL=00) O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) -6 2 Reset Video Reset Video
Production Data
Reset
-5 3
-4 4
-3 5
-2 6
-1 7
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 0
9 1
10 2
11 3
12 4
13 5
Figure 41 Modes 12 and 13 Input Signal Sampling
Reset Video Reset Video Reset Video
CCD Outputs Time (MCLK) Phase MCLK VSMP VS R S /CL (RESREF=2) O/P (DEL=00 O/P (DEL=01) O/P (DEL=10) O/P (DEL=11) 33 1 34 2
35 3
36 4
37 5
38 6
39 7
40 0
41 1
42 2
43 3
44 4
45 5
46 6
47 7
48 0
49 1
50 2
51 3
52 4
53 5
54 6
55 7
R
G R G R G R G
Figure 42 Modes 12 and 13 Output Data Timing
6 MCLK VSMP VS 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1
F CL (RESREF=0) R S /CL (RESREF=1) R S /CL (RESREF=2) R S /CL (RESREF=3) R S /CL (RESREF=4) R S /CL (RESREF=5) R S /CL (RESREF=6)
F Invalid RESREF positions in CDS mode (Mode 12)
Figure 43 Modes 12 and 13 Reset Sample/Clamp Positions
WOLFSON MICROELECTRONICS LTD
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WM8148 DEVICE CONFIGURATION
Production Data
The following section details the Control Register Map, the contents of which determines the operation of the WM8148, and the Control Bit table, which describes the possible settings of each of the bits in the Control Register Map.
INTERNAL REGISTER DEFINITION
Table 6 details the internal register contents. SET-UP REGISTER 1 * * * * * * * * * * Selects global power on/off or selective enable. Selects the function of the SDO pin. Controls input sampling mode the device is operating in.
SET-UP REGISTER 2 Enables individual sections of the device such as sample and hold blocks or PGA.
SET-UP REGISTER 3 Sets the clamp and reset sample position in CDS modes. Sets the clamp position in non-CDS modes. Enables the internal clocks to be free running without VSMP. Allows the video and reset sample pulse widths to be reduced by half an MCLK period. Selects the channel that the sample is taken from in One-Channel (or line by line) modes.
SOFTWARE RESET Writing to this register causes the device to reset. Three different reset types are available. See Control Bit Description Table for details.
SET-UP REGISTER 4 * * * * * * * * Allows the latency through the device to be adjusted by ADC clock periods and by half-MCLK periods. Enables VSMP as input or output. Allows the external setting of RLC bias reference voltage. Controls parallel/multiplexed output format. Defines the polarity of the output data.
COARSE OFFSETS Controls the non-CDS reference voltage level or reset clamp level. Allows external reference to be used as reset clamp level. Adjusts the d.c. level of the PGA outputs to align with the ADC input range to suit different input video signal polarities.
REVISION NUMBER * * Allows the user to check which revision of the device is being used.
DAC VALUES Programmes the amount of offset applied to the input of each PGA. Table 7 describes the sub-address bits for each channel.
PGA GAINS * Programmes the gain of each PGA. Table 7 describes the sub-address bits for each channel.
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WM8148
ADDRESS DESCRIPTION DEFAULT RW 000001 000010 000011 000100 000101 000110 000111 1000XY 1010XY Setup Register 1 Setup Register 2 Setup Register 3 Software Reset Setup Register 4 Coarse Offsets Revision Number DAC Values PGA Gains (HEX) 80 00 06 00 00 1B 43 80 00 RW RW RW W RW RW R RW RW B7
MODE[3] SENBL[7] CHAN[1] 0 INVOP 0 REV[7] DAC[7] 0
Production Data
BIT B6
MODE[2] SENBL[6] CHAN[0] 0 MUXOP PGAFS[1] REV[6] DAC[6] 0
B5
MODE[1] SENBL[5] SMALL 0 0 PGAFS[0] REV[5] DAC[5] PGA[5]
B4
MODE[0] SENBL[4] FREE 0 VSMPOP RLCEXT REV[4] DAC[4] PGA[4]
B3
SDO[1] SENBL[3] RESREF[3] 0 FDEL[1] RLCV[3] REV[3] DAC[3] PGA[3]
B2
SDO[0] SENBL[2] RESREF[2] 0 FDEL[0] RLCV[2] REV[2] DAC[2] PGA[2]
B1
SELEN SENBL[1] RESREF[1] SRES[1] DEL[1] RLCV[1] REV[1] DAC[1] PGA[1]
B0
EN SENBL[0] RESREF[0] SRES[0] DEL[0] RLCV[0] REV[0] DAC[0] PGA[0]
Note: Register address 000000 is reserved and should not be written to. Table 6 Control Register Map ADDRESS LSB DECODE Red register Green register Blue register Red, Green, and Blue registers X 0 0 1 1 Y 0 1 0 1
Table 7 Red, Green, Blue, Sub-address Bits
CONTROL BIT DESCRIPTION
CONTROL BIT/WORD Set-up Register 1 EN SELEN b0 b1 DEFAULT Address 000001 0 0 Global power on/off or selective enable. SELEN EN 0 0 Complete power down (default). 0 1 Complete power on. 1 X Individual block power on/off (X denotes either 1 or 0) see SENBL[7:0] register description for details. Multiplexes SDO output pin. SDO[1] SDO[0] 0 0 Register readback when requested, Hi-Z otherwise 0 1 TVIOL flag (RESREF inconsistent with MODE). 1 0 ADC over-range flag. 1 1 VSMP synchronous output. Device mode control bits. MODE[3] MODE[2] MODE[1] 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 MODE[0] 0 1 0 1 0 1 0 1 0 1 DESCRIPTION
SDO[1:0] b3, b2
00
MODE[3:0] b7, b6, b5, b4
1000
Three-channel (8-phase) CDS Three-channel (8-phase) non-CDS One-channel CDS One-channel non-CDS Two-channel (6-phase) CDS Two-channel (6-phase) non-CDS Three-channel (12-Phase) CDS Three-channel (12-Phase) non-CDS Two-channel (8-Phase) CDS Two-channel (8-Phase) non-CDS
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WM8148
CONTROL BIT/WORD Set-up Register 2 SENBL[7:0] b7.....b0 DEFAULT Address 000010 0000 0000 DESCRIPTION
Production Data
Selective power enable register, activated when SELEN = 1 (Set-up Register 1). Each bit activates respective cell when 1, de-activates when 0. SENBL[0] Bandgap/Bias SENBL[1] VRT, VRB buffers SENBL[2] VRX buffer SENBL[3] RLC DAC (allows VRLC to be externally driven) SENBL[4] Red S/H, PGA SENBL[5] Green S/H, PGA SENBL[6] Blue S/H, PGA SENBL[7] ADC
Set-up Register 3 RESREF[3:0] b3, b2, b1, b0 FREE b4
Address 000011 0110 Selects the position of either the reset sample and the clamp points in CDS modes, or the position of just the clamp pulse in non-CDS modes. See Mode Descriptions for further details. Enables internal clocks to be free running, without VSMP pulse input. FREE 0 Requires continuous VSMP pulse input every N periods of MCLK 1 Free running Reduces video and reset sample pulse widths by half an MCLK period. SMALL 0 Default pulse widths 1 Reduces pulse widths Selects the input channel in One-channel (line by line) modes. No effect when not in One-channel mode. CHAN[1] CHAN[0] 0 0 Red channel 0 1 Green channel 1 0 Blue channel 1 1 Reserved
0
SMALL b5
0
CHAN[1:0] b7, b6
00
Software Reset SRES[1:0] b1, b0
Address 000100 00 Writing to this register causes a software reset. There a three types of reset available: SRES[1] SRES[0] 0 0 Same action as NRESET pin 0 1 Resets all registers to default including RLCEXT. (Except EN, SELEN and SENBL[7:0], which are not changed) 1 X Resets PGA and DAC only (X denotes either 1 or 0)
Setup Register 4 DEL[1:0] b1, b0 FDEL[1:0] b3, b2
Address 000101 00 00 Adjusts the latency through the device in ADC clock periods. See Detailed Mode Timing Diagrams for details. Adjusts the latency through the device in half-MCLK increments. FDEL[1] FDEL[0] 0 0 Default position 0 1 Earlier by MCLK/2 1 0 Later by MCLK/2 Invalid in modes 0, 1, 4 and 5 1 1 Later by MCLK/2 Invalid in modes 0, 1, 4 and 5 In these invalid modes, output data is held constant, TVIOL is not flagged. Enables output of internally generated MCLK/N sync pulse (only if FREE also set). VSMPOP 0 Requires external VSMP 1 VSMP pin becomes sync output Reserved for Wolfson use only, must be programmed to 0.
VSMPOP b4
0
b5
0
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WM8148
CONTROL BIT/WORD MUXOP b6 DEFAULT 0 DESCRIPTION Changes the data output format from 12-bit parallel to 2 x 8 bit multiplexed. MUXOP 0 12-bit wide parallel data 1 8-bit wide multiplexed data
Production Data
INVOP b7
0
Digitally inverts the polarity of output data. INVOP 0 Negative-going video gives negative-going output data 1 Negative-going video gives positive-going output data
Coarse Offsets RLCV[3:0] b3, b2, b1, b0 RLCEXT b4
Address 000110 1011 Controls RLC DAC driving VRLC pin, to define single-ended signal-reference voltage or reset-level clamp voltage. F(hex) is VDD, 0(hex) is 0V, B(hex) (default) is 11/15 AVDD (= 3.67V typically). Powers down the RLC DAC, tri-stating its output, allowing VRLC to be externally driven. RLCEXT 0 RLC DAC drives VRLC pin 1 RLC DAC Hi-Z Configures the ADC input to accept the following video signal types: PGAFS[1] PGAFS[0] 0 0 Bipolar video 0 1 Bipolar video 1 0 Negative-going video 1 1 Positive-going video
1
PGAFS[1:0] b6, b5
00
Revision Number REV[7:0] b7, .....b0 DAC Values DAC[7:0] b7, .....b0 PGA Gains PGA[5:0] b5, ..... b0
Address 000111 43 Address 1000xy 1000 0000 Address 1010xy 000000 The gain setting data for the Red, Green, and Blue programmable gain amplifiers. 00(hex) gives min gain, 3F(hex) gives max gain. The offset-setting data for the Red, Green and Blue offset DACs. 00(hex) gives -200mV offset referred to signal input, FF(hex) gives +200mV, 80(hex) (default) gives approximately zero offset. Read-only register, allows the user to determine the revision level of the device. ASCII 7-bit code, e.g. 43(hex) = C
Table 8 Control Register Bit Descriptions
WOLFSON MICROELECTRONICS LTD
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WM8148 RECOMMENDED EXTERNAL COMPONENTS
DVDD 1 13 C1 C2 8 24 DGND 4 26 41 28 27 3 C3 C4 C5 C6 AVDD
Production Data
DVDD1 DVDD2
AVDD1 AVDD2 AVDD3
DGND1 DGND2 DGND3 DGND4
AVDD4
VRLC VRX
33 32 31
AGND
36
RINP GINP BINP
VRT
Video Inputs
37 39
C7 29 C11 38 23 22 AGND C12
C8 C9 C10
VRB
5
MCLK VSMP RLC
NC NC
Timing Signals
7 2
AGND
WM8148
NC
46 47 45
SCK/RNW SEN/STB SDI/DNA PNS
OP11 OP10 OP9 OP8 OP7
21 20 19 18 17 16 15 14 12 11 10 9 DVDD AVDD
Interface Controls
48
+ C13 + C14 + C15 + C16
43 42 34
OEB NRESET OVRD
OP6 OP5 OP4 OP3
Output Data Bus
DGND
AGND
35 N O T E S : 1. C1-12 should be fitted as close to WM8148 as possible. 2. AGND and DGND should be connected as close to WM8148 as possible. 40 30 25 6
AGND1 AGND2 AGND3 AGND4 AGND5
OP2 OP1 OP0
SDO
44
Serial Output
AGND
Figure 44 External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 SUGGESTED VALUE 10nF 10nF 10nF 10nF 10nF 10nF 10nF 1F 100nF 100nF 100nF 100nF 1F 1F 1F 1F DESCRIPTION De-coupling for DVDD1. De-coupling for DVDD2. De-coupling for AVDD4. De-coupling for AVDD3. De-coupling for AVDD2. De-coupling for AVDD1. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRX. De-coupling for VRLC. De-coupling for VRB. De-coupling for VRT. Reservoir capacitor for DVDD. Reservoir capacitor for DVDD. Reservoir capacitor for AVDD. Reservoir capacitor for AVDD.
Table 9 External Components Descriptions WOLFSON MICROELECTRONICS LTD
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WM8148 APPLICATIONS RECOMMENDATIONS
INTRODUCTION
Production Data
The WM8148 is a mixed signal device, therefore careful PCB layout is required. The following section contains PCB layout guidelines, which are recommended for optimal performance from the WM8148, and some typical applications circuits.
PCB LAYOUT
1) 2) 3) 4) Use separate analogue and digital power and ground planes. The analogue and digital ground planes should be connected as close as possible to, or underneath, the WM8148. Place all supply decoupling capacitors as close as possible to their respective supply pins and provide a low impedance path from the capacitors to the appropriate ground. Avoid noise on AGND (in particular on pins 30, 35 and 40). Avoid noise on reference pins VRT, VRB and VRX. Place the decoupling capacitors as close as possible to these pins and provide a low impedance path from the capacitors to analogue ground. Input signals should be screened from each other and from other sources of noise to avoid cross talk and interference. Minimise load capacitance on digital outputs. Capacitive loads of greater than 20pF will degrade performance. Use buffers if necessary and keep tracks short.
5) 6)
TYPICAL APPLICATIONS DIAGRAMS
CCDs are available in four basic types that are all compatible with the WM8148. * * * * Monochrome single output. Monochrome odd-even output. Colour 3 output. Colour 6 output.
Each of these applications is outlined in this section. The output from a CCD sensor usually has a high impedance and must therefore be buffered as close to the sensor as possible. The sensor manufacturers' datasheets specify the buffer circuit to use. Initially, the designer must decide if CDS and Reset Level Clamping is to be used. The WM8148 supports both of these functions and Wolfson recommend using both CDS and pixel-by-pixel clamping for optimal performance. In this case a low value a.c. coupling capacitor is required between the sensor and the WM8148. Experiments have shown that a 100pF capacitor is the optimum value to use, however this may vary for particular applications depending on speed of operation and PCB layout.
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WM8148
MONOCHROME SINGLE OUTPUT
Production Data
S E N S O R
C V OUT BUFFER See sensor datasheet for details RINP
WM8148
Including recommended external components
CLOCKS
DATA
SYSTEM ASIC
CONTROL I/F SENSOR TIMING
Maximum Pixel Rate = 6.66Mpixels/second (Mode 2)
Figure 45 Block Diagram of Monochrome CCD Application REGISTER DESCRIPTION Set-up register 1 Set-up register 2 Set-up register 3 ADDRESS 000001 000010 000011 HEX 22 9F 02 SETTING BINARY 0010 0010 1001 1111 0000 0010 MODE: Mode 2: single-channel CDS SELEN: selective power enable SENBL: green/blue PGAs powered off CHAN: red channel selected RESREF: reset sample half-way between video samples INVOP: invert digital output (White = 4095) PGAFS: ADC set up for negative polarity video RLCEXT, RLCV: internal VRLC voltage, set to 3.7V NOTE
Set-up register 4 Coarse offsets
000101 000110
80 4B
1000 0000 0100 1011
Table 10 Typical Control Register Settings for Figure 45 (CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 6)
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WM8148
MONOCHROME ODD-EVEN OUTPUT
Production Data
S E N S O R
CO O BUFFER RINP
CLOCKS
WM8148
Including DATA recommended external components CONTROL I/F
CE E BUFFER See sensor datasheet for details. GINP
SYSTEM ASIC
SENSOR TIMING
Maximum Pixel Rate = 10.66Mpixels/second (Mode 4) Maximum Pixel Rate = 12Mpixels/second (Mode 12)
Figure 46 Block Diagram of Monochrome CCD (Odd-Even Outputs) Application REGISTER DESCRIPTION Set-up register 1 Set-up register 2 Set-up register 3 Set-up register 4 Coarse offsets ADDRESS 000001 000010 000011 000101 000110 HEX 42 BF 02 80 4B SETTING BINARY 0100 0010 1011 1111 0000 0010 1000 0000 0100 1011 MODE: Mode 4: Two-channel CDS SELEN: selective power enable SENBL: blue PGAs powered off RESREF: reset sample half-way between video samples INVOP: invert digital output (White = 4095) PGAFS: ADC set up for negative polarity video RLCEXT, RLCV: internal VRLC voltage, set to 3.7V NOTE
Table 11 Typical Control Register Settings for Figure 46 (CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 6) REGISTER DESCRIPTION Set-up register 1 Set-up register 2 Set-up register 3 ADDRESS 000001 000010 000011 HEX C2 BF 02 SETTING BINARY 1100 0010 1011 1111 0000 0010 MODE: Mode 12: Two-channel CDS SELEN: selective power enable SENBL: blue PGAs powered off CHAN: red channel selected RESREF: reset sample half-way between video samples INVOP: invert digital output (White = 4095) PGAFS: ADC set up for negative polarity video RLCEXT, RLCV: internal VRLC voltage, set to 3.7V NOTE
Set-up register 4 Coarse offsets
000101 000110
80 4B
1000 0000 0100 1011
Table 12 Typical Control Register Settings for Figure 46 (CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 8)
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WM8148
COLOUR 3 OUTPUT
Production Data
CR
S E N S O R
R
BUFFER CG
RINP
CLOCKS
WM8148
GINP Including recommended external components DATA
G
BUFFER CB
B
BUFFER See sensor datasheet for details.
BINP
CONTROL I/F
SYSTEM ASIC
SENSOR TIMING
Maximum Pixel Rate = 4Mpixels/second (Modes 0 and 8)
Figure 47 Block Diagram of Colour CCD Application REGISTER DESCRIPTION Set-up register 1 ADDRESS 000001 HEX 01 SETTING BINARY 0000 0001 MODE: Mode 0: Three-channel CDS (8-phase) SELEN, EN: fully enabled Default (don't care) RESREF: reset sample half-way between video samples INVOP: invert digital output (White = 4095) PGAFS: ADC set up for negative polarity video RLCEXT, RLCV: internal VRLC voltage, set to 3.7V NOTE
Set-up register 2 Set-up register 3 Set-up register 4 Coarse offsets
000010 000011 000101 000110
00 04 80 4B
0000 0000 0000 0100 1000 0000 0100 1011
Table 13 Typical Control Register Settings for Figure 47 (CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 8) REGISTER DESCRIPTION Set-up register 1 ADDRESS 000001 HEX 81 SETTING BINARY 1000 0001 MODE: Mode 8: Three-channel CDS (12-phase) SELEN, EN: fully enabled Default (don't care) RESREF: reset sample half-way between video samples INVOP: invert digital output (White = 4095) PGAFS: ADC set up for negative polarity video RLCEXT, RLCV: internal VRLC voltage, set to 3.7V NOTE
Set-up register 2 Set-up register 3 Set-up register 4 Coarse offsets
000010 000011 000101 000110
00 06 80 4B
0000 0000 0000 0110 1000 0000 0100 1011
Table 14 Typical Control Register Settings for Figure 47 (CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 12)
WOLFSON MICROELECTRONICS LTD
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41
WM8148
COLOUR 6 OUTPUT
Production Data
For applications that require higher pixel rates, multiple WM8148 devices can be used. The following diagrams show typical configurations.
C RE RE BUFFER C GE GE BUFFER C BE GINP RINP CLOCKS
WM8148
Including DATA recommended external components CONTROL I/F
S E N S O R
BE
BUFFER
BINP
CRO RO BUFFER CGO GO BUFFER C BO BO BUFFER See sensor datasheet for details. BINP GINP RINP CLOCKS
SYSTEM ASIC
WM8148
Including DATA recommended external components CONTROL I/F
SENSOR TIMING
Figure 48 Block Diagram Showing Dual Architecture
C RE RE BUFFER CRO RO BUFFER GINP RINP
WM8148
Including recommended external components
CLOCKS DATA
CONTROL I/F
S E N S O R
C GE GE BUFFER CGO GO BUFFER GINP RINP
WM8148
Including recommended external components
CLOCKS DATA
CONTROL I/F
SYSTEM ASIC
C BE BE BUFFER C BO BO BUFFER See sensor datasheet for details. GINP RINP
WM8148
Including recommended external components
CLOCKS DATA
CONTROL I/F
SENSOR TIMING
Figure 49 Block Diagram Showing Triple Architecture WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
42
WM8148 PACKAGE DIMENSIONS
FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C
Production Data
b
e
25
36
37
24
E1
E
48
13
1
12
c
D1 D
L
A
A2
A1 -Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (Millimeters) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 3.5 7 0 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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PD Rev 4.0 April 1999
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